Technical Field
The present invention generally relates to formation of a fuse structure from a vertical fin, and more particularly to vertically integrated addressable fuse elements as part of a fuse array.
Description of the Related Art
Fuses can be used in semiconductor circuits for various purposes, for example, redundancy circuits in memory arrays and devices, and programming of programmable logic arrays. Fuses have typically been implemented in semiconductors using polysilicon or metal as the fuse material. A blown fuse shows a very large increase in resistance. Current to blow such fuses can be exceptionally large, and electro-migration can cause a conductive path to be reformed across a blown metal fuse.
Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and finFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain. The channel for the finFET can be an upright slab of thin rectangular Si, commonly referred to as the fin with a gate on the fin, as compared to a typical planar FET with a single gate parallel to the plane of the substrate. Depending on the doping of the source and drain, an n-FET or a p-FET can be formed.